Processor architecture/features trump "number of cores" in terms of power consumption.
The 1st generation QSD8650 in the EVO is built with a 65nm process. It was already more power efficient than the stock Cortex-A8, especially at higher (notably, overclocked) clock frequencies. The second generation was a die-shrink with a few additional features thrown on -- a 45nm process that consumed over 30% less power at the same clock rate (even more at higher ones, and it has been clocked to nearly 2Ghz by enthusiasts). The third generation Snapdragon uses the same (albeit again slightly tweaked) Scorpion core, but [un-]coupled to another. Unlike stock Cortex-A9 dual-core rivals (the likes of Tegra, Exynos, etc), there are additional power-saving benefits in the 3rd generation snapdragon -- dynamic independent clock units that apparently scale dynamically according to a hardware-polled (kernel-dictated) metric -- either to the max each core allows or via a similar scheme to Intel's new Turbo Boost, which can theoretically clock each processor both independently and to a core-scaled maximum according to TDP (in Intel's case) or total clock (in Qualcomm's case) constraints.
That is, depending on your kernel's governor, you can set the processor to clock up to a certain "configuration" -- dependent on core use -- that aims for a fixed maximum or average power consumption. Think about it this way (and it's still in the air as to what the stock/HTC kernel uses as a governor, though my bets are on lowpassed core-independent Linux 2.6.35 'ondemand'). This particular snapdragon, therefore, can potentially (though it probably isn't the default) realize the following clock governing example along a continuum:
- Core 0 100% load case, Core 1 0% load: 1.5Ghz (1497MHz, the chipset's actual safe factory maximum, see MDP) on Core 0 and 245MHz/off for Core 1.
- Core 0 and Core 1 simultaneously 100% load: Both cores clocked at 998Mhz.
Both situations would be expected to produce similar power draw profiles, not accounting for additional architectural changes, the efficiency/latency of the polling method, voltage considerations across the two cores, energy dissipation, etc etc...
It's a much more complex world than some unibody concept of "single core" versus some hypothetical end-all "dual core" processor. Coupled with other design considerations (including software, battery, build, screen, other hardware components), these other chipset and governor considerations relegate such an overly generalized "power draw" distinction to oblivion, happily enough. So rest easy, folks. Once this thing comes out and custom builds/kernels are compiled, we'll all have the time of our lives.
