static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 0, 24576,SRC_LPXO, 0, 0, 30720000, 900, VDD_RAW(900) },
{ 0, 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) },
{ 1, 122880, PLL_3, 5, 5, 61440000, 900, VDD_RAW(900) },
{ 0, 184320, PLL_3, 5, 4, 61440000, 900, VDD_RAW(900) },
{ 1, 245760, PLL_3, 5, 2, 61440000, 900, VDD_RAW(900) },
{ 1, 368640, PLL_3, 5, 1, 122800000, 900, VDD_RAW(900) },
{ 1, 460800, PLL_1, 2, 0, 153600000, 900, VDD_RAW(900) },
{ 1, 576000, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
{ 1, 652800, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
{ 1, 768000, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
{ 1, 806400, PLL_2, 3, 0, UINT_MAX, 1000, VDD_RAW(1000), &pll2_tbl[0]},
{ 1, 921600, PLL_2, 3, 0, UINT_MAX, 1000, VDD_RAW(1000), &pll2_tbl[1]},
{ 1, 1024000, PLL_2, 3, 0, UINT_MAX, 1000, VDD_RAW(1000), &pll2_tbl[2]},
{ 1, 1113000, PLL_2, 3, 0, UINT_MAX, 1050, VDD_RAW(1050), &pll2_tbl[3]},
{ 1, 1209600, PLL_2, 3, 0, UINT_MAX, 1100, VDD_RAW(1100), &pll2_tbl[4]},
{ 1, 1305600, PLL_2, 3, 0, UINT_MAX, 1150, VDD_RAW(1150), &pll2_tbl[5]},
{ 1, 1401600, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[6]},
{ 1, 1516800, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[7]},
{ 1, 1612800, PLL_2, 3, 0, UINT_MAX, 1300, VDD_RAW(1350), &pll2_tbl[8]},
{ 0, 1708800, PLL_2, 3, 0, UINT_MAX, 1350, VDD_RAW(1350), &pll2_tbl[9]},
{ 0, 1804800, PLL_2, 3, 0, UINT_MAX, 1350, VDD_RAW(1350), &pll2_tbl[10]},
{ 0, 1900800, PLL_2, 3, 0, UINT_MAX, 1450, VDD_RAW(1450), &pll2_tbl[11]},